Abstract: In this paper, we propose a low computational complexity MIMO detector with K-best algorithm that can select K value adaptively. It combines distributed K-Best (DKB) and successive interference cancellation (SIC) algorithms to reduce visiting nodes. The proposed K-value adjusting mechanism is proposed to decide the number of possible candidates at each searching stage. Instead of calculating the SNR level, the proposed adaptively adjusting algorithm compares the similarity of minimum PED and next minimum PED to decide K-value. It can achieve much lower computational complexity than conventional K-best architecture without descending the BER performance. Applying with recursive pipelined circuit architecture, the proposed MIMO detector supports various antenna configurations and data modulations from 2x2 to 8x8 and 64-QAM to QPSK, respectively. The proposed circuit is fabricated in 90nm CMOS process with core area of 0.546mm2. The maximum throughput is 126Mbps at operating clock of 127MHz, and the power consumption is 20.6mW under 1V power supply.

Abstract: This paper describes the design and simulation of new combined antenna using a probe-fed Planar Inverted-F Antenna (PIFA) with rectangular patch in the same substrate operates from 9 GHz to 10.66GHz. The polarization diversity is realized by this structure, its becomes one of the most important techniques than can be used, the main reason for this conception is that the method does not require any extra bandwidth or physical separations between the antennas. The simulation allowed the characterization of the designed antenna and the computing of different antenna parameters like S11 parameters, resonant frequency, bandwidth, directivity . The combined element is analyzed and the simulation results are presented . The results are very interesting.

Abstract: In this paper, a complete super-regenerative QPSK receiver is designed to operate at 2.4 GHz while being able to properly receive, process and demodulate incoming signal into raw digital data. The receiver front-end is comprised of an LNA and a super-regenerative oscillator (SRO), both merged for current reuse and lower power consumption. The front-end is followed by a simple signal conditioning circuit that uses SRO oscillations to generate four phase digital clocks to clock a novel, yet simple digital phase detection engine that is capable of demodulating phase modulation preserved in SRO oscillations into original sent data. The whole receiver was designed using a 0.13 um technology, where simulation results show a power consumption of only 0.87 mW, while being able to properly detect and demodulate a -90 dBm, 4 Mbps QPSK modulated signal equivalent to 0.22 nj/b.